This application claims the priority benefit of Taiwan application serial no. 91120950, filed Sep. 13, 2002.
1. Field of the Invention
The invention relates in general to a pixel structure of a thin-film transistor (TFT) liquid crystal display (LCD), and more particularly, to a pixel structure of a low-temperature polysilicon thin-film transistor liquid crystal display (LTPS TFT-LCD) with a high aperture ratio.
2. Related Art of the Invention
The LTPS TFT-LCD is different from conventional amorphous (a-Si) TFT-LCD in that the electron mobility is over 200 cm2/V-sec and the smaller area meets the requirement of high aperture ratio. Therefore, problems of reduction of brightness and overall power consumption of the display are resolved in the LTPS TFT-LCD. In addition, the increase of electron mobility integrates a part of the driver circuit and the thin-film transistor on the same glass substrate, such that the reliability of the LCD panel is significantly improved. Therefore, the fabrication cost of the LTPS TFT-LCD is much less than that of the conventional a-Si TFT-LCD. In addition, the LTPS TFT-LCD further has the advantages of thinness, light weight, high resolution and can be applied to power-saving and mobile products.
Referring to FIG. 1, in a pixel structure of a conventional TFT-LCD, a storage capacitor is composed of a pixel electrode and a scan line. The pixel structure of the TFT-LCD comprises a pixel 100, a scan line 106 for driving the pixel 100, and a signal line 108 for driving the pixel 100. The pixel 100 comprises a thin-film transistor 102 and a pixel electrode 104. The thin-film transistor 102 comprises a gate 102a and a source/drain region 102b. In the thin-film transistor 102, the gate 102a and the scan line 106 are electrically connected. The source/drain region 102b has one side connected to the signal line via the plug 112a and the other side connected to the pixel electrode 104 via the plugs 112b and 114.
In addition, the pixel electrode 104 is located in a region between the neighboring signal lines 108 and the neighboring scan lines 106, 106a, while a portion of the pixel electrode 104 overlaps with the adjacent scan line 106a to form a storage capacitor 110. The capacitance of the storage capacitor 110 is determined according to the overlapping area of the pixel electrode 104 and the scan line 106a, and the thickness of the dielectric layer (not shown) formed between the pixel electrode 104 and the scan line 106a. 
Referring to FIG. 2, a schematic drawing of a storage capacitor composed of a pixel electrode and a common line of a pixel structure of a conventional TFT-LCD is shown. The pixel structure comprises a pixel 200, a scan line 206 for driving the pixel 200, and a signal line for driving the pixel 200. The pixel 200 is composed of a thin-film transistor 202 and a pixel electrode 204, while the thin-film transistor 202 comprises a gate 202a and a source/drain region 202b. In the thin-film transistor 202, the gate 202a is electrically connected to the scan line 206, and one side of the source/drain region 202b is electrically connected to the signal line 208 via the plug 212a and the other side connected to the pixel electrode 204 via the plugs 212b and 214.
In addition, a common line 216 is formed on the region between the neighboring scan lines 206, and the pixel electrode 204 is formed on the region between the neighboring signal line 208 and the neighboring scan line 206. The overlap between the pixel electrode 208 and the common line 216 constructs a storage capacitor 210. The capacitance of the storage capacitor 210 is determined according to the area of the overlap of the pixel electrode 204 and the common line 216, and the thickness of the dielectric layer (not shown) formed between the pixel electrode 204 and the common line 216.
In the storage capacitor structure constructed by the pixel electrode and the scan line, a very broad line width of the scan line is reserved to obtain sufficient capacitance. This causes the problem of reduced aperture ratio. The same problem exists for the storage capacitor formed by the pixel electrode and the common line.
In addition, the fringe field between the neighboring pixels causes the rearrangement of the liquid crystal molecules; and consequently, results in pixel fringe leakage. Therefore, a black matrix (BM) has to be formed on the opposing substrate, that is, the color filter substrate, to shield the leakage area. The black matrix formed on the color filter substrate also reduces the aperture ratio.
The present invention provides a pixel structure of low-temperature polysilicon thin-film transistor liquid crystal display with a high aperture ratio.
The low-temperature polysilicon thin-film transistor liquid crystal display provided by the present invention comprises a pixel, a scan line, a signal line and a storage capacitor. The pixel comprises a low-temperature polysilicon thin-film transistor and a pixel electrode. The scan line and the signal line are used to drive the low-temperature polysilicon thin-film transistor. The storage capacitor comprises a doped polysilicon layer, a dielectric layer and a shielding metal layer and is electrically connected to the pixel electrode.
The above doped polysilicon layer of the storage capacitor and the polysilicon layer of the low-temperature polysilicon thin-film transistor are defined in the same step. The shielding metal layer does not only have the light-shielding function, but also functions to form the storage capacitor by coupling the doped polysilicon layer.
In the present invention, the low-temperature polysilicon layer has a gate and a source/drain region. The gate is electrically connected to the scan line. One side of the source/drain region is electrically connected to the signal line, and the other side of the source/drain region is electrically connected to the pixel electrode. In addition, the source/drain region includes N-type or P-type dopant.
In the present invention, the shielding metal layer includes molybdenum-tungsten alloy, chromium, molybdenum or other material with both shielding and conductive effects. The shielding metal layer does not overlap with the signal line; and therefore, no parasitic capacitor is induced between the shielding metal layer and the signal line.
In the present invention, the storage capacitor is located under the signal line. The doped polysilicon layer has an opening located under the signal line. The formation of the opening allows the overlapping region of the doped polysilicon layer and the signal line to be reduced, such that the parasitic capacitance between the doped polysilicon layer and the signal line is consequently reduced.
The doped polysilicon layer of the storage capacitor includes N-type or P-type dopants. In addition, the doped polysilicon layer is connected to a common voltage Vcom.